1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, more particularly to a master-slice-type semiconductor integrated circuit device including a plurality of logic circuits.
2. Description of the Related Art
Master-slice-type semiconductor integrated circuit (IC) devices are advantageous in that they allow the fast, efficient production of smaller lots of diverse semiconductor IC devices.
In the master-slice manufacturing method, a set of mask patterns common for various semiconductor IC devices is designed. Using this set of common mask patterns, a large number of semifinished devices are manufactured by a common process. This process stops with the diffusion step. Each semifinished device has the same circuit element cells, each including at least one logic circuit, such as an OR gate, and at least one current source, for driving the logic circuit. Using the semifinished devices, the desired finished devices are then produced by a predetermined wiring process which operatively connects the mutual circuit cells and connects the circuit cells and input/output portions to obtain a specific connection pattern. Thus, various semiconductor IC devices, having desired circuit constructions, can be easily formed.
Normally, a semiconductor IC device has hundreds to thousands of circuit element cells. Therefore, a large number of wiring connections are required. For this purpose, wiring channels are arranged around the circuit element cells. The higher the density of the semiconductor IC device, the smaller the wiring channel region and the more complex the wiring connection. Therefore, in the prior art semiconductor IC devices, there are strict requirements imposed on wiring design, such as minimizing the connection wire length in consideration of the spatial relationship between the circuit element cells and the space of the wiring channels and preventing the occurrence of inconnectable circuit element cells on the chip, which result in low efficiency of utilization of the semiconductor IC device.
Prior art master-slice-type semiconductor IC devices particularly suffer from insufficient design flexibility for forming the desired circuit combinations, since certain logic gates and certain current sources are standardly formed in each circuit element cell for possible connection in the cell. This lack of design flexibility further reduces the rate of utilization of the circuit element cells of the prior art master-slice-type semiconductor IC devices.
Similarly, prior art master-slice-type semiconductor IC devices suffer from complicated arrangements of power feeding means. Each power feeding means forms two layers, each consisting of a plurality of parallel conductive strips. The parallel strips of the higher and lower layers of each power feeding means intersect perpendicularly with each other to form a lattice like-structure. This has the disadvantages of low manufacturing efficiency and complicated wiring connection.